The present invention relates to a low spurious charge pump for low phase noise phase locked loops (PLL). Such a charge pump can be used in analog PLL design, solid state circuits, ASIC, integrated circuits, etc.
IEEE paper “A 1.4 gHz Differential Low noise CMOS Frequency Synthesiser using a wideband PLL architecture” from the authors Li Lin et al. published at the 2000 IEEE International Solid State Circuits conference describes PLL charge pumps which are built around a simple cascoded current source. Such a PLL charge pump is schematically shown in appended FIG. 1. Any variation of the voltage of the drain node A1 or B1 of the current source transistor M10 or M20 due to a variation of the output voltage is limited by the cascode transistor M40 or M60. A switch transistor M30, M50 placed in parallel with a cascode transistor, respectively M40, M60 is deviating or not the current pumped by M10 or injected by M20 according to the control signal.
This method allows to control that the current of M10 or M20 is well pumped from or injected to the output node or not. Despite the presence of the cascode transistors M40, M60, this pumping or injection of will induce a change on the voltage on the node A1 or B1. This will generate some voltage transients on the node and consequently spurious on the output current.